1. Field of the Invention
The present invention relates to a semiconductor device and a process of producing the same, and particularly, to a semiconductor device having a first electronic part and a second electronic part, the first electronic part being larger than the second electronic part in area and in the number of connection terminal pads including pad-form electrode terminals, the first and second electronic parts being disposed one upon the other with the respective pad forming surfaces facing each other, and the external connection terminals or other connection terminals being bonded to the connection terminal pads, and a process of producing the same.
2. Description of the Related Art
FIG. 16 shows a semiconductor device 100, having two semiconductor chips 102 and 104 disposed one upon the other, which has been recently brought into practical use. The semiconductor chip 102 having a smaller area is mounted on, and bonded to, one side of the semiconductor chip 104 having a larger area.
The smaller semiconductor chip 102 has one side, or an electrode terminal forming surface, provided with electrode terminals 112 formed thereon and electrically connected, via conductor wires 110, to connection pads 108 formed on a substrate 106 and has another side, or a surface which is opposite to the electrode terminal forming surface and is bonded to one side of the larger semiconductor chip 104.
The larger semiconductor chip 104 has one side bonded to the smaller semiconductor chip 102 and provided with electrode terminals 114 formed thereon and electrically connected, via conductor wires 110, to connection pads 108 formed on the substrate 106 and has another side bonded to one side of the substrate 106 on which side connection pads 108 are formed.
The substrate 106 has the other side provided with external connection terminals or bumps 116 to be connected to connection pads of a motherboard.
The device 100 having the semiconductor chips 102 and 104 on the substrate is sealed or packaged with a sealing or packaging resin 118 to form a package.
The semiconductor device 100 shown in FIG. 16 advantageously provides an electronic system having an improved operating speed and performance in comparison with a system assembled of separate semiconductor packages having respective semiconductor chips 102 and 104, because not only is the delay of the signal transfer between chips 102 and 104 significantly mitigated but also the influence of the capacitance and inductance throughout the system is suppressed.
However, the conventional semiconductor device 100 has a drawback that electrode terminals cannot be formed on the surfaces of the chips 102 and 104 in the portion for bonding the chips to each other, so that the chip 104 must have a portion on which electrode terminals are disposed in the surface bonded to the chip 102 for bonding the conductor wires 110.
Furthermore, to mount a chip capacitor or other passive element on the semiconductor chip 104, an area therefor must be also provided in the surface bonded to the chip 102.
Therefore, miniaturization of the semiconductor chip 104 has an unavoidable limit.
Moreover, the presence of the substrate 106 makes it difficult to reduce the thickness of the device 100 as a whole.
There is also a drawback that it is difficult to transfer an assembly of the chips 102 and 104 by vacuum adsorption or other usual transfer means and handling in the production process is complicated, because of the presence of the electrode terminals 112 and 114 exposed from the upper surfaces of the chips 102 and 104.
The object of the present invention is to provide a semiconductor device having a first electronic part and a second electronic part, the first electronic part being larger than the second electronic part in area and in the number of connection terminal pads including pad form electrode terminals, the first and second electronic parts being disposed one upon the other with respective pad forming surfaces facing each other, and external connection terminals or other connection terminals being bonded to the connection terminal pads, and a process of producing the same, in which the semiconductor device can be easily miniaturized and reduced in thickness.
To achieve the object according to the present invention, there is provided a semiconductor device having a first electronic part and a second electronic part, the first electronic part being larger than the second electronic part in area and in the number of connection terminal pads including pad form electrode terminals, and external connection terminals or other connection terminals being bonded to the connection terminal pads, wherein:
the first and second electronic parts are disposed one upon the other with respective pad forming surfaces facing each other and are electrically connected to each other by flip-chip bonding; and
springy wire-form connection terminals stand on, and are bonded to, the connection terminal pads of the first electronic part other than those electrically connected to the connection terminal pads of the second electronic part.
Because the first and second electronic parts are flip-chip bonded to each other, neither conductor wires nor connection pads therefor are necessary for electrical connection between the two parts, so that the delay of the signal transfer is minimized and so that the first electronic part larger in area need not have a portion on which electrode terminals are disposed in the surface bonded to the second electronic part, for bonding the conductor wires, and therefore, the degree of freedom in designing the electronic parts is increased.
The springy wire-form connection terminals allow the semiconductor device to be directly mounted on, and electrically connected to, a motherboard without an intervening substrate conventionally used, thereby enabling the thickness of the semiconductor device to be reduced.
The springy nature of the wire-form connection terminals also advantageously prevents occurrence of a thermal stress which would otherwise occur because of a difference in thermal expansion coefficient between the semiconductor device and the motherboard, or conventionally between the first electronic part and the substrate.
In a preferred embodiment, the second electronic part includes a semiconductor chip to provide a minimized delay in the signal transfer between the semiconductor chips of the first and second electronic parts.
In another preferred embodiment, the first electronic part is a chip size package having substantially the same size as that of a semiconductor chip mounted thereon and/or the second electronic part is either a bare chip having electrode terminals in a pad form or a chip size package having substantially the same size as that of a semiconductor chip mounted thereon. This further facilitates miniaturization of the semiconductor device.
In another preferred embodiment, the connection terminal pads are electrically connected to electrode terminals of a semiconductor chip through extension wiring formed on an electrode terminal forming surface of the semiconductor chip to allow the connection terminal pads to be disposed entirely over the electrode terminal forming surface.
In another preferred embodiment, the connection terminal pads are composed of two layers of different metals etchable with different etchants to enable the connection terminal pads for external connection to be formed by electrolytic plating and etching.
In another preferred embodiment, the springy wireform connection terminals are composed of a bent wire of gold or other metal having a metal coating plated thereon to provide reinforced springy wire-form connection terminals.
The present invention also advantageously ensures miniaturization and reduction in thickness of the semiconductor device, when the second electronic part is a passive element such as a chip capacitor or a chip resistor having electrode terminals electrically connected to the connection terminal pads of the first electronic part.
According to the present invention, there is also provided a process of producing a semiconductor device having a first electronic part and a second electronic part, the first electronic part being larger than the second electronic part in area and in number of connection terminal pads including pad form electrode terminals, the first and second electronic parts being disposed one upon the other with respective pad forming surfaces facing each other, the first and second electronic parts being electrically connected to each other by flip-chip bonding, and external connection terminals or other connection terminals bonded to the connection terminal pads, the process comprising the steps of:
providing a wafer having a plurality of chip size packages formed therein as the first electronic parts, the chip size packages having substantially the same size as that of a semiconductor chip mounted thereon;
electrically connecting the first electronic parts with the second electronic parts by flip-chip bonding; and
cutting the wafer to separate the chip size packages from each other, each of the chip size packages having the second electronic part flip-chip bonded thereto.
The process also provides a minimized delay in the signal transfer between the semiconductor chips of the first and second electronic parts of the semiconductor device in various embodiments as follows.
In one embodiment, the second electric part is a bare chip having pad form electrode terminals as connection terminal pads.
In another embodiment, the second electric parts are also chip size packages having substantially the same size as that of a semiconductor chip mounted thereon, and the first and second electronic parts are electrically connected by bonding the connection terminal pads thereof via connection terminals formed on the connection terminal pads of one of the first and second electronic parts.
In another embodiment, prior to the step of electrically connecting the first and second electronic parts by flip-chip bonding, the process further comprises the step of electrically connecting the connection terminal pads to electrode terminals of a semiconductor chip mounted on a chip size package formed in the wafer, through an extension wiring formed on an electrode terminal forming surface of the semiconductor chip. This allows the connection terminal pads to be disposed in a desired portion on one side of the chip size package, which is typically formed as the first electronic part.
In another preferred embodiment, prior to the step of electrically connecting the first and second electronic parts by flip-chip bonding, the process further comprises the step of:
bonding bent wires of gold or other metal to the connection terminal pads in a selected portion of the first electronic parts formed in the wafer;
plating the bent wires to form a metal layer thereon to provide springy wire form external connection terminals standing on the connection terminal pads; and
electrically connecting the second electronic part to the connection terminal pads in a portion other than the selected portion of the first electronic part.
This facilitates miniaturization and a reduction in thickness of the semiconductor device of the present invention.
In another preferred embodiment, the connection terminal pads composed of two layers of different metals etchable with different etchants can be easily formed by the steps of forming a first metal layer on a wafer to entirely cover a pad forming surface of the wafer, forming on the first metal layer a second metal layer having a selected pattern and etchable with an etchant different from an etchant which etches the first metal layer by electrolytic plating using the first metal layer as a plating current supply layer, and removing the first metal layer in a portion not covered with the second metal layer by etching.
The present invention also facilitates handling of an assembly of the first and second electronic parts in the production process, because the first and second electronic parts are flip-chip bonded to each other to provide the assembly with a smooth upper surface suited to vacuum adsorption or other usual transfer means.
The present inventive process is also advantageous because a plurality of chip size packages are formed in a wafer having a high degree of flatness which enables high precision forming of connection pads, etc. of the respective chip size packages and because the second electronic parts are flip-chip bonded to the respective chip size packages on the wafer to facilitate precise positioning and bonding of the second electronic parts with respect to the chip size packages.